Physical Unclonable Functions are used for authenticating hardware devices. This paper discusses implementing a pseudo-linear feedback shift register-based Physical Unclonable Function on an Artix-7 device within the Basys-3 Field Programmable Gate Array development board. The primary goal is to create an area efficient Physical Unclonable Function that generates more challenge-response pairs than conventional pseudo linear feedback shift register-based designs. The design relies on a linear feedback shift register but uses combinational circuits such as inverters and XOR gates instead of shift registers. The strength of the Physical Unclonable Function is based on the quantity of challenge-response pairs it generates, with a larger set indicating better security. The proposed design produces a large-bit response within a stipulated area, capturing n bits of response from a single n-bit challenge. Additionally, the mapping of challenge and response pairs can be varied without altering the hardware structure. Typically, Physical Unclonable Functions are implemented on Field Programmable Gate Arrays and Application Specific Integrated Circuits. This study details the design of a robust linear feedback shift register-based Physical Unclonable Function and how the modified design increases challenge response pairs within a given area on Field Programmable Gate Array fabric.