With the rapid advancement of technology, the number of processing cores integrated on a single chip known as System on Chip (SoC) has grown enormously. The continuing growth of these cores raises the need for efficient on-chip communication since the existing bus interconnecting them is only scalable to a certain extent and cannot meet the communication demands of the future SoCs. Network on Chip (NoC) has emerged as a promising and a viable solution for the design of future SoCs. It overcomes the scalability, high delay and high power dissipation problems of the bus-based communication by interconnecting the cores through a network. Using a network provides better scalability, high performance and low power consumption. Due to these advantages, researchers from academia and industry have been motivated to design many NOC architectures. An 8 degree Mesh based NoC architecture (M8NOC), has recently been proposed. A preliminary analytical model shows that it can achieve better performance compared to other architectures. However, the results obtained from the analytical model do not consider wiring length, wiring budget, and pins out constraints. This research aims to develop a new simulation model to better evaluate the performance of the M8NoC architecture using an OMNeT++ based simulator. The average throughput and the average end-to-end delay were used as the main metrics to evaluate the performance of the M8NoC. Numerous experiments have been conducted for different parameters like network size, injection rate, channel width, and packet size. Several combinations of these parameters have been investigated and compared with those of mesh architecture. The investigation reveals that the M8NoC outperforms mesh due to its high node degree, small diameters and large bisection width.